The present invention relates generally to a clock supply circuit and a data transfer circuit utilizing the clock supply circuit.
In recent years, the operating clock frequencies of integrated circuits have been remarkably improved, and application specific integrated circuits (ASICs), such as gate arrays and standard cells, which have an operating clock frequency of about 500 MHz, have been developed. This value of operating clock frequency is about 50 times as large as that of ten years ago, and contributes to the improvement of degree of integration of circuits and the expansion of application.
However, with the increase in operating clock frequency, the number of problems to be solved increases. The problems include measures against clock skews. The clock skew is a phenomenon caused by the fact that the phase difference between a clock signal and a data signal is different every part of an integrated circuit, and a phenomenon for causing the malfunction of the circuit when a data signal in a switching transient state or a data signal at a time different from a predetermined timing is stored in a resistor which is a backup memory for data signals. It is impossible to quantitatively analyze a clock skew until the layout of an integrated circuit is completed, and the resulting phenomenon is uncertain, so that it is often difficult to find a clock skew causing malfunction and it is often difficult to take measures to cope with the clock skew even if it is found. Conventionally, as measures taken to cope with the clock skew, the following two means have been adopted.
FIG. 1 is a schematic diagram for explaining first conventional clock skew eliminating means. In the first conventional clock skew eliminating means, a grid-like clock supply dedicated wiring 11 having buffers 2 on the input side of respective clock supply paths is provided to supply only a clock signal P0 via the clock supply dedicated wiring 11 to reduce the phase difference between a data signal and the clock signal P0 every part of an integrated circuit.
The first conventional clock skew eliminating means is particularly effective in integrated circuits, such as gate arrays and field programmable gate arrays (FPGAs), wherein the arrangement of circuits in the whole chip is previously determined. For example, as shown in the drawing, the grid-like clock supply dedicated wiring 11 is provided, so that it is possible to control a clock skew on the chip to be less than a certain value.
FIG. 2 is a schematic diagram for explaining second conventional clock skew eliminating means. In the second conventional clock skew eliminating means, a plurality of second stage buffers 2xe2x80x2 are provided on the output side of a first stage buffer 2 provided in a clock supply path, and a plurality of third stage buffers 2xe2x80x3 are provided on the output side of each of the second stage buffers 2xe2x80x2. Thus, a clock wiring branching at some stages of buffers is provided to design a circuit so that the output loads of the respective stages of buffers are as equally as possible. A plurality of stages of flip-flops 6 are connected to the downstream sides of the respective third stage buffers 2xe2x80x3.
The first and second conventional clock skew eliminating means are often combined. However, there are the following problems in the above described first and second conventional clock skew eliminating means.
As described above, the first conventional clock skew eliminating means, i.e., the method using the clock supply dedicated wiring, is particularly effective in an integrated circuit wherein the arrangement of the circuit in the whole chip has been determined. However, in the case of an integrated circuit, such as a standard cell, wherein the arrangement of the circuit in the whole chip has not been determined at the first stage, it is difficult to design an ideal circuit since the arrangement of the clock supply dedicated wiring is designed at the same time that or after the arrangement of other signal lines is designed. Thus, the clock skew depends on the resulting layout. Therefore, there is a problem in that there are some cases where the clock skew can not be suppressed to be less than a required predetermined value.
In the second conventional clock skew eliminating means, e.g., in the method using a branching clock wiring for designing the circuit so that the output loads of the buffers in the respective stages are as equally as possible, it is required to design the clock wiring on the basis of engineer""s manual calculation if the clock wiring is designed before the layout of the arrangement of the circuit, so that the engineer must very carefully design the clock wiring for a long time. On the other hand, if the circuit is automatically designed by means of a computer, the clock wiring is designed after the layout of the arrangement of the circuit. Therefore, there are problems in that it takes a long time to modify the layout of the arrangement of the circuit, and there are some cases where it is required to do over the layout of the whole chip again, so that the design is complicated so as not to be adopted to automation and it takes a long period of time to design the circuit.
As described above, the malfunction of a circuit due to clock skews is caused by the phase difference between a clock signal and a data signal. This is a local phenomenon in a chip by nature. However, the conventional clock skew eliminating means are designed to reduce the maximum value of the phase difference in a clock signal itself at the respective parts, and this reduction is carried out over the whole integral circuit. Therefore, there is a great waste of design from the standpoint of the prevention of malfunction.
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide a clock supply circuit which can prevent the malfunction of a circuit from being caused by clock skews and which can be applied to the design of various integrated circuits, and a data transfer circuit utilizing the clock supply circuit.
In order to accomplish the aforementioned and other objects, according to a first aspect of the present invention, there is provided a clock supply circuit for supplying clock signals to a data transfer circuit, which comprises a plurality of stages of cascade-connected data signal input/output circuits and wherein the plurality of stages of data signal input/output circuits from a data signal input stage to a data signal output stage are divided into a plurality of groups, each including predetermined stages of the data signal input/output circuits, the clock supply circuit supplying a more phase-lagged clock signal to one of the data signal input/output circuits belonging to a group nearer the data signal input stage of the plurality of stages of data signal input/output circuits out of the plurality of groups.
Specifically, according to the first aspect of the present invention, there is provided a clock supply circuit for supplying clock signals to a data transfer circuit, which comprises a plurality of stages of cascade-connected data signal input/output circuits and wherein the plurality of stages of data signal input/output circuits from a data signal input stage to a data signal output stage being divided into a plurality of groups, each including predetermined stages of the data signal input/output circuits, wherein the clock supply circuit comprises a plurality of stages of buffers connected in series, the clock supply circuit supplying a clock signal, which is one of a plurality of clock signals derived from any one of the plurality of stages of buffers on the basis of an input clock signal and which is derived via a more number of stages of buffers, to a data signal input/output circuit belonging to a group nearer the data signal input stage of the plurality of stages of data signal input/output circuits out of the plurality of groups.
With this construction, the phase of the clock signal inputted to the transmit side data signal input/output circuit does not pass the phase of the clock signal inputted to the receive side data signal input/output circuit, so that each of the data signal input/output circuits can always acquire the ascertained data signal. As a result, it is possible to prevent the malfunction of the circuit due to clock skews. In addition, the clock supply circuit according to the first aspect of the present invention can achieve the above described function with simple construction and can be easily designed, so that the clock supply circuit can be applied to the design of various integrated circuits.
According to a second aspect of the present invention, there is provided a clock supply circuit for supplying clock signals to each of a plurality of stages of data signal input/output circuits and an output control signal generating circuit of a data transfer circuit, which comprises: the plurality of stages of data signal input/output circuits divided into a plurality of groups, each including predetermined stages of the data signal input/output circuits; a data bus serving as a transfer path for a data signal outputted from one of the data signal input/output circuits belonging to any one of the groups; the output control signal generating circuit, provided in each of the groups, for generating an output control signal for controlling the data signal outputted from the one of the data signal input/output circuits to the data bus for each of the groups; and a data signal selecting circuit for selecting any one of a data signal on the data bus and the data signal outputted from the one of the data signal input/output circuits, as a data signal to be inputted to the one of the data signal input/output circuits, wherein the clock supply circuit supplies a clock signal, which is phase-lagged from a clock signal supplied to each of the data signal input/output circuits, to the output control signal generating circuit.
Specifically, according to the second aspect of the present invention, there is provided a clock supply circuit for supplying clock signals to each of a plurality of stages of data signal input/output circuits and an output control signal generating circuit of a data transfer circuit, which comprises: the plurality of stages of data signal input/output circuits divided into a plurality of groups, each including predetermined stages of the data signal input/output circuits; a data bus serving as a transfer path for a data signal outputted from one of the data signal input/output circuits belonging to any one of the groups; the output control signal generating circuit, provided in each of the groups, for generating an output control signal for controlling the data signal outputted from the one of the data signal input/output circuits to the data bus for each of the groups; and a data signal selecting circuit for selecting any one of a data signal on the data bus and the data signal outputted from the one of the data signal input/output circuits, as a data signal to be inputted to the one of the data signal input/output circuits, wherein the clock supply circuit comprises a plurality of stages of buffers connected in series, the clock supply circuit supplying a clock signal, which is one of a plurality of clock signals derived from any one of the plurality of stages of buffers on the basis of an input clock signal and which is derived via the most number of stages of buffers, to the output control signal generating circuit.
With this construction, the phase of the clock signal inputted to the output control signal generating circuit for outputting the output control signal for controlling the output of the data signal to the data bus is always lagged from the phase of the clock signal inputted to each of the data signal input/output circuits for mutually transferring the data signal. Therefore, each of the data signal input/output circuits for mutually transferring the data signal can acquire a predetermined data signal before the data signal on the data bus varies, so that it is possible to completely prevent the malfunction of the circuit due to clock skews. In addition, the clock supply circuit according to the second aspect of the present invention can achieve the above described function with simple construction and can be easily designed, so that the clock supply circuit can be applied to the design of various integrated circuits.
In the clock supply circuit according to the first or second aspect of the present invention, the following construction may be applied.
The phase difference between the most phase-advanced clock signal and the most phase-lagged clock signal, out of the plurality of clock signals, each of which is supplied so as to have a phase difference from each other, on the basis of the input clock signal may be less than one period of the input clock signal. Thus, each stage of data signal input/output circuit can acquire a predetermined data signal at each timing.
In addition, the clock signal supply wiring for supplying the clock signals to the plurality of stages of data signal input/output circuit may be provided so as to pass through the plurality of stages of data signal input/output circuits. Thus, it is possible to prevent clock skews from being caused by the difference in wiring length from the clock buffers to the data signal input/output circuits or the like, so that it is possible to completely prevent the malfunction of the circuit due to clock skews. Moreover, part or all of the plurality of stages of buffers may be provided in the plurality of stages of data signal input/output circuits.
According to a third aspect of the present invention, a data transfer circuit comprises: a plurality of stages of cascade-connected data signal input/output circuits, the plurality of stages of data signal input/output circuits from a data signal input stage to a data signal output stage being divided into a plurality of groups, each including predetermined stages of the data signal input/output circuits; and a clock supply circuit for supplying a more phase-lagged clock signal to a data signal input/output circuit belonging to a group nearer the data signal input stage of the plurality of stages of data signal input/output circuits out of the plurality of groups.
Specifically, according to the third aspect of the present invention, the data transfer circuit comprises: a plurality of stages of cascade-connected data signal input/output circuits, the plurality of stages of data signal input/output circuits from a data signal input stage to a data signal output stage being divided into a plurality of groups, each including predetermined stages of the data signal input/output circuits; and a clock supply circuit comprising a plurality of stages of buffers connected in series, the clock supply circuit supplying a clock signal, which is one of a plurality of clock signals derived from any one of the plurality of stages of buffers on the basis of an input clock signal and which is derived via a more number of stages of buffers, to a data signal input/output circuit belonging to a group nearer the data signal input stage of the plurality of stages of data signal input/output circuit out of the plurality of groups.
With this construction, the phase of the clock signal inputted to the transmit side data signal input/output circuit does not pass the phase of the clock signal inputted to the receive side data signal input/output circuit, so that each of the data signal input/output circuits can always acquire the ascertained data signal. As a result, it is possible to prevent the malfunction of the circuit due to clock skews. In addition, the clock supply circuit of the data transfer circuit according to the third aspect of the present invention can achieve the above described function with simple construction and can be easily designed, so that the clock supply circuit can be applied to the design of various integrated circuits.
According to a fourth aspect of the present invention, a data transfer circuit comprises: a plurality of stages of data signal input/output circuits divided into a plurality of groups, each including predetermined stages of the data signal input/output circuits; a data bus serving as a transfer path for a data signal outputted from one of the data signal input/output circuits belonging to any one of the groups; an output control signal generating circuit, provided in each of the groups, for generating an output control signal for controlling the data signal outputted from the one of the data signal input/output circuits to the data bus for each of the groups; a data signal selecting circuit for selecting any one of a data signal on the data bus and the data signal outputted from the one of the data signal input/output circuits, as a data signal to be inputted to the one of the data signal input/output circuits; and a clock supply circuit a clock signal, which is phase-lagged from a clock signal supplied to each of the data signal input/output circuits, to the output control signal generating circuit.
Specifically, according to the fourth aspect of the present invention, the data transfer circuit comprises: a plurality of stages of data signal input/output circuits divided into a plurality of groups, each including predetermined stages of the data signal input/output circuits; a data bus serving as a transfer path for a data signal outputted from one of the data signal input/output circuits belonging to any one of the groups; an output control signal generating circuit, provided in each of the groups, for generating an output control signal for controlling the data signal outputted from the one of the data signal input/output circuits to the data bus for each of the groups; a data signal selecting circuit for selecting any one of a data signal on the data bus and the data signal outputted from the one of the data signal input/output circuits, as a data signal to be inputted to the one of the data signal input/output circuits; and a clock supply circuit comprising a plurality of stages of buffers connected in series, the clock supply circuit supplying a clock signal, which is one of a plurality of clock signals derived from any one of the plurality of stages of buffers on the basis of an input clock signal and which is derived via the most number of stages of buffers, to the output control signal generating circuit.
With this construction, the phase of the clock signal inputted to the output control signal generating circuit for outputting the output control signal for controlling the output of the data signal to the data bus is always lagged from the phase of the clock signal inputted to each of the data signal input/output circuits for mutually transferring the data signal. Therefore, each of the data signal input/output circuits for mutually transferring the data signal can acquire a predetermined data signal before the data signal on the data bus varies, so that it is possible to completely prevent the malfunction of the circuit due to clock skews. In addition, the clock supply circuit of the data transfer circuit according to the fourth aspect of the present invention can achieve the above described function with simple construction and can be easily designed, so that the clock supply circuit can be applied to the design of various integrated circuits.
In the data transfer circuit according to the third or fourth aspect of the present invention, the following construction may be applied.
The phase difference between the most phase-advanced clock signal and the most phase-lagged clock signal, out of the plurality of clock signals, each of which is supplied so as to have a phase difference from each other, on the basis of the input clock signal may be less than one period of the input clock signal. Thus, each stage of data signal input/output circuit can acquire a predetermined data signal at each timing.
In the clock supply circuit, the clock signal supply wiring for supplying the clock signals to the plurality of stages of data signal input/output circuit may be provided so as to pass through the plurality of stages of data signal input/output circuits. Thus, it is possible to prevent clock skews from being caused by the difference in wiring length from the clock buffers to the data signal input/output circuits or the like, so that it is possible to completely prevent the malfunction of the circuit due to clock skews. Moreover, part or all of the plurality of stages of buffers may be provided in the plurality of stages of data signal input/output circuits.